[Solved]-False "Combinational loop detected"-scala

It obviously depends on your specific code but I would still suggest trying to avoid creating the false combinational loop. It is likely true that it is a false loop, but tools like Verilator will likely struggle with it as well.

That being said, you can disable the check by passing --no-check-comb-loops to the FIRRTL step of compilation (also known as the Verilog-generation step). In rocket-chip, it depends on which simulation directory you're doing, but in vsim it is here, in emulator it is here.