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it obviously depends on your specific code but i would still suggest trying to avoid creating the false combinational loop. it is likely true that it is a false loop, but tools like verilator will likely struggle with it as well.

that being said, you can disable the check by passing --no-check-comb-loops to the firrtl step of compilation (also known as the verilog-generation step). in rocket-chip, it depends on which simulation directory you're doing, but in vsim it is here, in emulator it is here.


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